top_module_phase2 Project Status (03/14/2012 - 12:33:51)
Project File:	Phase2b.xise	Parser Errors:	No Errors
Module Name:	Actuate	Implementation State:	Synthesized
Target Device:	xc3s1000-5fg676	Errors:
Product Version:	ISE 13.4	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Out of Date	Wed 14. Mar 10:07:13 2012
WebTalk Log File	Out of Date	Wed 14. Mar 10:07:25 2012

Date Generated: 03/14/2012 - 12:33:51