main Project Status (10/10/2011 - 12:09:54)
Project File: imperial_daqtest.xise Parser Errors: No Errors
Module Name: main Implementation State: Programming File Generated
Target Device: xc3s1000-5fg676
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
19 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 57 15,360 1%  
Number of 4 input LUTs 73 15,360 1%  
Number of occupied Slices 61 7,680 1%  
    Number of Slices containing only related logic 61 61 100%  
    Number of Slices containing unrelated logic 0 61 0%  
Total Number of 4 input LUTs 73 15,360 1%  
Number of bonded IOBs 61 391 15%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.07      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 10. Oct 12:05:13 201103 Warnings (0 new)0
Translation ReportCurrentMon 10. Oct 12:49:57 2011016 Warnings (0 new)64 Infos (0 new)
Map ReportCurrentMon 10. Oct 12:50:06 2011003 Infos (0 new)
Place and Route ReportCurrentMon 10. Oct 12:50:30 2011001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon 10. Oct 12:50:35 2011004 Infos (0 new)
Bitgen ReportCurrentMon 10. Oct 12:50:47 2011001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri 7. Oct 15:15:55 2011
WebTalk ReportCurrentMon 10. Oct 12:50:48 2011
WebTalk Log FileCurrentMon 10. Oct 12:50:54 2011

Date Generated: 01/26/2012 - 20:13:19